1. Field of the Invention
The present invention relates to a method of screening semiconductor devices in order to improve the product reliability in the process of manufacturing semiconductor devices such as MOS LSI circuits, in particular.
2. Description of the Prior Art
In the MOD LSI circuits, the products easy to be broken down tend to be defective in a short service time, thus causing a serious problem in the reliability of the MOS circuits. To overcome this problem, the MOS LSI products are usually screened before shipment from the factory. In the screening, a voltage higher than the voltage applied in use is applied to MOS LSI products assembled into a package for acceleration test, in order to previously remove the samples easy to be broken down.
An example of the prior art screening method is disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 64-7633. In this prior art screening method, a wafer is prepared on which polycrystal gate electrodes are formed on gate oxide films for a group of transistors arranged on the same chip area; after an insulating layer has been deposited on this wafer, the deposited insulating layer is patterned to expose gate electrode portions; after that a metallic layer has been deposited on the exposed portions, a metallic layer is patterned so that only gate electrode portions of a group of transistors to be tested can be covered simultaneously; a voltage is applied between the metallic layer and the wafer to pass current through the respective gate oxide film at the same time; and when an abnormally large current flows, the gate oxide film is determined to be abnormal.
In the above-mentioned prior art screening method, however, since the gate electrodes of a group of transistors formed on the same chip are connected to each other by a patterned metallic layer, in the case where P-channel MOS transistors and N-channel MOS transistors are both included in the same LSI circuits, it has been difficult to detect the defective elements.
In more detail, in the semiconductor devices of this type, since any of the P-channel MOS transistors and the N-channel MOS transistors, e.g., P-channel MOS transistors are formed in wells, when the voltage is applied on the basis of the N-channel MOS transistors, a voltage drop at the PN junction between the well and the substrate is relatively large, so that a sufficient high screening voltage cannot be applied to the gate oxide film of the P-channel MOS transistors, with the result that it has been difficult to detect the abnormality at the gate oxide film within the well.
Further, when the screening voltage is applied, in spite of the fact that there exists a problem in that the gate oxide film deteriorates or the lifetime of the gate oxide film is shortened, nothing has been taken into account of this problem.